IES5501 Questions
Why do I need a bus buffer in my 2-wire bus application?
What bus standards can the IES5501 bus buffer operate with?
Can we use the IES5501 in SMBus High Power Mode?
Can I use the IES5501 bus buffer for hot insertion applications?
Why does the IES5501 bus buffer not need a rise-time accelerator?
What are the disadvantages of Rise-time-accelerators?
What is the difference between a bus buffer and a bus repeater?
How does using Bipolar design techniques make the IES5501 better than CMOS type Bus Buffers?
Is there a minimum bus capacitance required for the IES5501 bus buffer to operate?
Can I level shift from 1.8V to 15V?
Can I connect the bus buffers in series to expand my bus?
Can I use the IES5501 to use 2 or more masters on a bus?
What pull-up resistors do I need on the inputs and outputs?
Do I need additional capacitors on the inputs and outputs of a bus buffer?
Can I use the IES5501 at a transmission speed of 1Mhz?
What happens on the outputs if there is no power to the IES5501?
Can I use the IES5501 bus buffer at TTL logic levels?
Can the IES5501 be used in radial ATCA systems? IES5502 Questions Why do I need a bus buffer in my 2-wire bus application?
What does it mean for the IES5502 to be a ‘Dual bi-directional unity gain buffer’
What bus standards can the IES5502 bus buffer operate with?
Can we use the IES5502 in SMBus High Power Mode?
Can I use the IES5502 bus buffer for hot insertion applications?
Why does the IES5502 bus buffer not need a rise-time accelerator?
What are the disadvantages of Rise-time-accelerators?
How does using Bipolar design techniques make the IES5502 better than CMOS type Bus Buffers?
Can I level shift from 1.8V to 15V using the IES5502?
Can I connect the IES5502 bus buffers in series to expand my bus?
Can I use the IES5502 to use 2 or more masters on a bus?
Can I use the IES5502 at a transmission speed of 1Mhz?
Why is the Ready output pin “open collector”?
What happens on the outputs if there is no power to the IES5502?
Can I use the IES5502 bus buffer at TTL logic levels? Top Why do I need a bus buffer in my 2-wire bus application?
Bus buffers extend the amount of capacitative load which can be applied to the bus, allowing the addition of more components or longer wiring connections. It is particularly appropriate for interfacing at backplanes. Top What bus standards can the IES5501 bus buffer operate with?
The IES5501 will operate in bus systems using the Standard and Fast Mode I2C TM Bus, and the Standard and High Power SMBus, as well as other bus systems based on similar principles (eg PMBus). Alternately, the IES5501 will operate beyond this specification to allow the user to define their own optimal bus condition - e.g. A 15V bus between two IES5501 buffers. Top Can we use the IES5501 in SMBus High Power Mode?
Yes. The IES5501 will sink the 4mA bus current of the SMBus High Power mode. Top Can I use the IES5501 bus buffer for hot insertion applications?
Yes. The enable pin on the buffer can be controlled by a microprocessor, watchdog, or even a simple RC circuit. This enables bus communications after power has stabilised on the inserted board. It will not interfere with bus signals whilst it is powering up. Top Why does the IES5501 bus buffer not need a rise-time accelerator?
Rise time accelerators have been avoided on this design due to the problems that they can introduce into the system. The IES5501 will quickly transfer signals on the bus under an impressive range of voltage, current and load conditions, while providing better noise margins and not introducing glitches. Top What are the disadvantages of Rise-time-accelerators?
Rise-time accelerators can quickly turn small noise perturbations into full rail spikes on the bus. Other devices are then burdened with the responsibility of filtering the spikes introduced by buffers containing these circuits. The complex circuits involved in these accelerators reduce noise margins on the bus, and add cost and complexity to the system. Top What is the difference between a bus buffer and a bus repeater?
Repeaters will attempt to interpret highs and lows on the bus, and pass this signal to the output. To avoid latch-up, the output low of one repeater cannot be interpreted as an input low to another repeater. Therefore repeaters cannot be placed in series, restricting the architecture of the system. Buffers will not try to interpret highs and lows, but will instead track the voltage level on each side of the buffer. They therefore act in an analogue nature. Top How does using Bipolar design techniques make the IES5501 better than CMOS type Bus Buffers?
Advanced high-speed bipolar technology allows the IES5501 to make quick decisions about which side of the buffer is in control. Other buffers commonly suffer significant glitches when control passes from one side of the buffer to the other, whereas the IES5501 will show negligible effects even under the worst possible conditions. Top Is there a minimum bus capacitance required for the IES5501 bus buffer to operate?
No. Some small level of capacitance may improve system performance under some conditions, but this is often inherent in most designs. Top Can I level shift from 1.8V to 15V?
Yes, or anywhere in between. Top Can I connect the bus buffers in series to expand my bus?
Yes. Two or even more buffers can be placed in series due to the excellent input-output offset voltage characteristics, and the good noise immunity of the input threshold. Top Can I use the IES5501 to use 2 or more masters on a bus?
The IES5501 does not impose any restrictions on the bus specification. Two masters can be used anywhere on either side of the buffer. Top What pull-up resistors do I need on the inputs and outputs?
The pull-up resistance depends upon the bus voltage used. The buffer will operate with bus currents between 100µA and 4mA. Top Do I need additional capacitors on the inputs and outputs of a bus buffer?
No. Some small level of capacitance may improve system performance under some conditions, but this is often inherent in most designs. Top Can I use the IES5501 at a transmission speed of 1Mhz?
Yes, although the maximum capacitance of the bus would be reduced. This is not a restriction of the buffer, but of the “RC” nature of this type of bus system. Top What happens on the outputs if there is no power to the IES5501?
The outputs are high impedance. No load or interference is applied to the bus. Top Can I use the IES5501 bus buffer at TTL logic levels?
While not using TTL logic levels itself, the IES5501 will interface to TTL devices. The buffer will track (with some small input-output offset) any signal applied to it's I/O pins which fall below 33% of the IC's supply voltage. Therefore, as long as VIN + VOFFSET < TTL low level, the system is compatible. Top Can the IES5501 be used in radial ATCA systems?
Thanks to the IES5501, radial architectures are now the ideal solution to IPMB implementation in ATCA systems, with high noise margins; individually enabled, capacitively isolated radial arms; and a very cost affordable solution. IES5502 FAQ Top Why do I need a bus buffer in my 2-wire bus application?
Bus buffers extend the amount of capacitative load that can be applied to the bus, allowing the addition of more components or longer wiring connections. It is particularly appropriate for interfacing at backplanes. Top What does it mean for the IES5502 to be a ‘Dual bi-directional unity gain buffer’
There are two (dual) buffers in the IES5502 package, one each for SDA and SCL. These buffer's are bi-directional, allowing the signaling on an I2C TM style bus to travel in both directions – that is, Masters and Slaves can be placed anywhere on either side of the buffer. The buffer is not a logic device with set 'hi' and 'lo' states, but instead it is an analogue amplifier (with a gain of 1) where the output tracks the input signal (with a small voltage offset). Top What bus standards can the IES5502 bus buffer operate with?
The IES5502 will operate in bus systems using the Standard and Fast Mode I2C TM Bus, and the Standard and High Power SMBus, as well as other bus systems based on similar principles (eg PMBus). Alternately, the IES5502 will operate beyond this specification to allow the user to define their own optimal bus condition - e.g. A 15V bus between two IES5502 buffers. Top Can we use the IES5502 in SMBus High Power Mode?
Yes. The IES5502 will sink the 4mA bus current of the SMBus High Power mode. Top Can I use the IES5502 bus buffer for hot insertion applications?
The IES5502 contains “hot-insertion” logic that will look for “bus-idle” or “stop” conditions within a signaling sequence, making it ideal for hot-insertion applications. This will mean the buffer will not be enabled through a part-transmission, ensuring the integrity of the data. Where staggered (longer supply, shorter bus) connections are used on a plug-in board, the IC will also “charge” the bus pins to 1-volt prior to connection, assisting in the elimination of glitches on contact. Top Why does the IES5502 bus buffer not need a rise-time accelerator?
Rise time accelerators have been avoided on this design due to the problems that they can introduce into the system. The IES5502 will quickly transfer signals on the bus under an impressive range of voltage, current and load conditions, while providing better noise margins and not introducing glitches. Extremely low cost discrete circuits can easily be added to perform the rise-time accelerator function (refer to application note AN103). Top What are the disadvantages of Rise-time-accelerators?
Rise-time accelerators can quickly turn small noise perturbations into full rail spikes on the bus. Other devices are then burdened with the responsibility of filtering the spikes introduced by buffers containing these circuits. The complex circuits involved in these accelerators reduce noise margins on the bus, and add cost and complexity to the system. Top How does using Bipolar design techniques make the IES5502 better than CMOS type Bus Buffers?
Advanced high-speed bipolar technologies allow the IES5502 to make quick decisions about which side of the buffer is in control. Other buffers commonly suffer significant glitches when control passes from one side of the buffer to the other, whereas the IES5502 will show negligible effects even under the worst possible conditions. Top Can I level shift from 1.8V to 15V using the IES5502?
Yes, or anywhere in between. Top Can I connect the IES5502 bus buffers in series to expand my bus?
Yes. Two or even more buffers can be placed in series due to the excellent input-output offset voltage characteristics, and the good noise immunity of the input threshold. Top Can I use the IES5502 to use 2 or more masters on a bus?
The IES5502 does not impose any restrictions on the bus specification. Two masters can be used anywhere on either side of the buffer. Top Can I use the IES5502 at a transmission speed of 1Mhz?
The IES5502 can run at 1MHz bus frequency (not FM+). The maximum bus frequency will be limited by the load capacitance of each segment – the IES5502 can help you increase this frequency, by dividing the capacitance up into smaller segments. Top Why is the IES5502 Ready output pin “open collector”?
This allows the ready outputs of multiple devices to be connected in wired-and (wired-or) configuration, and thus a single “READY” signal can be connected to the input of the master device (eg. Micro-controller), from many buffers. Top What happens on the outputs if there is no power to the IES5502?
With no supply voltage, the outputs of the IES5502 will be high impedance. Top Can I use the IES5502 bus buffer at TTL logic levels?
While not using TTL logic levels itself, the IES5502 will interface to TTL devices. The buffer will track (with some small input-output offset) any signal applied to it's I/O pins which fall below 33% of the IC's supply voltage. Therefore, as long as VIN + VOFFSET < TTL low level, the system is compatible.
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