IES5502 - dual bi-directional bus buffer with hot insertion logic
IES5502 extends and expands your I2C, 2-Wire, SMBus, PMBus, IPMB Using analog design principles, the IES5502 is a true dual bi-directional bus buffer for use in 2-wire bus systems such as I˛CTM, SMBusTM, PMBusTM & IPMB or other systems where hot insertion logic for detecting stop and idle conditions is required for live insertion into backplanes. The IES5502 significantly increases system noise margins on the Intelligent Platform Management Bus (IPMB) and is excellent for implementing cost effective IPMB architectures. The hot insertion feature also makes them ideal for use on Intelligent Platform Management Controller (IPMC) boards. The unique operation of the IES5502 provides one of the fastest response times of such bi-directional buffers as it does this without the need for ‘rise-time accelerators'. The use of rise-time accerators when combined with low noise margins may cause glitches outside the I2C specification.
features
Dual bi-directional unity gain buffer Hot insertion logic prevents data and clock bus corruption for live backplane applications Pre-charge minimizes data corruption on live insertion Open collector ready output Fully I2C compliant & supports a wide range of 2-wire standards Doesn’t impose additional restrictions on logic levels Very low input to output offset voltages Multiple bus buffers allowed in cascade, multi-drop or “daisy chain” fashion	Compatible with all other classes of 2-wire bus buffer Wide range of allowed bus voltages (1.8V to 15V) Level shifting between bus voltages (1.8V to 15V) Superior response times Plugs in to live backplanes Chip enable allows bus disconnection No minimum bus capacitance requirement Low current stand-by mode when not enabled Application/removal of power to IC will not interfere with other bus activity Available in SO-8 and MSOP-8
applications
Telecommunications Systems (inc. ATCATM) Radial IPMB architectures Power Management System Backplane Management / Interconnect Desktop and Portable Computers (inc. RAID) Compact PCIRExpress	2-Wire Bus Switch/Multiplexing Applications Automotive Accessories (up to 15V) Building Automation TV / Projector / Monitor interconnection Game Consoles / Boxes TV / Projector / Monitor interconnection Game Consoles / Boxes Gaming Machine Networks
IES5502 bus buffer description
The IES5502 bus buffer (Fig 1) is compatible for extending I2C, SMBus, PMbus and other similar 2-wire bus systems where hot insertion into live backplanes and optimum performance is required. They feature hot insertion logic for detecting stop and idle conditions, pre-charge and a very low input to output offset voltages, allowing buffer cascading and increasing system reliability. The IES5502 significantly increase system noise margins on the intelligent platform management bus (IPMB) and are excellent for implementing cost effective IPMB architectures. The IES5502 bus buffer extends the bus load limit by buffering both the Clock (SCL) and Data (SDA) lines. It supports up to 400 pF loads on each side of the buffer at 400kHz. Higher capacitance is supported at lower speeds, and lower capacitance at higher speeds up to 1MHz. The unique operation of the IES5502 provides one of the fastest response times of such bi-directional buffers, ensuring any glitches (common to other buffers) are kept well within the 50 ns I2C specification. The wide allowable voltage range expands their potential in ATCA and CompactPCI power management systems, backplane management systems and for bus voltage level translation (1.8V to 15V).
I2CTM is a trademark of Philips Semiconductors Corporation SMBusTM and PMBusTM are trademarks of System Management Interface Forum (SMIF) Inc ATCATM PICMGR CompactPCIRExpress are Registered trademarks of PCI Industrial Computers Manufacturers Group